The present invention relates generally to semiconductor memory devices, and, more particularly, to static random access memory (SRAM) cell array structures.
SRAM has been a memory staple for a long time, due to its simple operation, high access speed and low power dissipation, etc. SRAM's simple operation comes from its bi-stable cells, meaning it can maintain its state indefinitely without refreshing as needed by dynamic random access memory (DRAM), as long as an adequate power is supplied.
One well-known conventional structure of a SRAM cell has six transistors (6T) that are constructed as a pair of pass-gate transistors and two cross-coupled inverters. Here the ‘cross-coupled’ means one inverter's output connected to the other inverter's input, so they form a latch circuit with bi-stable states. Each inverter comprises a NMOS pull-down transistor and a PMOS pull-up transistor. Conventionally, sources and bulks of the pull-up transistors are coupled to a positive power supply, or Vdd. Sources and bulks of the pull-down transistors as well as bulks of the pass-gate transistors are connected to ground, or Vss. The inverter's outputs serve as two storage nodes, when one is pulled low, the other is pulled high. A complementary bit-line pair is coupled to the pair of storage nodes via the pair of pass-gate transistors, respectively. The gates of the pass-gate transistors are commonly connected to a word-line. When the word-line voltage is switched to Vdd, the pass-gate transistors are turned on, so the storage nodes are accessible by the bit-line pair. When the word-line voltage is switched to Vss, the pass-gate transistors are turned off, so the storage nodes are essentially isolated from the bit lines, although some leakage occurs. But as long as the Vdd is maintained above a certain level, the state of the storage nodes is maintained indefinitely.
But with scaling of MOSFET dimensions deep down into deep submicron range, many new factors begin to seriously affect memory chip performance. For one thing, a system voltage that is lower than 1.0V is too close to transistor threshold voltage (Vt). Another factor is random dopant and device size fluctuations. All these factors impact particularly static noise margin (SNM) in SRAM, which causes loss in yield.
Smaller device size and lower power dissipation require the lowering of the system voltage. But SRAM accessing speed, stability and reliability require an adequate voltage. They are contradictory goals, and limit traditional SRAM's performances.
What is desired is an improved design to achieve substantial read/write noise margin through varying pull-up transistor voltage supply. By de-coupling source and bulk, the voltage supply to the sources can swing more easily.